This present disclosure relates to systems and methods for preventing defects in microelectronic integrated circuits (IC) and particularly, a low voltage IC test system and method for defect screening of ICs for the purposes of preventing defects in microelectronic circuits from getting into the field where they can cause reliability fails.
Depending on where a defect lands in the fabrication of semiconductors it is possible that the defect can cause shorting from power to ground and not affect signal lines (e.g., “shorts defects”). Thus an impacted chip can be fully functional and pass all structural and functional testing. These chips can then be sorted as a good and sold into the field. In the field the defect can continue to draw current and create localized heating. The current drawn can create increased levels of electromigration and other reliability problems. Localized heating can then, over time, damage the shorted circuit as well as microelectronic circuits in its vicinity.
Many reliability failure mechanisms are accelerated through higher temperatures, for instance electromigration (which for instance Cu is sensitive to) where electron current moves metal atoms, time dependent dielectric breakdown, stress migration, and NBTI (Negative Bias Temperature Instability).
The problem of latent electrical current drawing defects in IC's that do not create a logic fail can become reliability fails in the future (resulting in RE fails due to defect growth or by resistive/Joule heating of the surrounding circuitry accelerating other temperature driven fail modes and by electromigration), is getting more important to solve as wiring dimensions continue to shrink. Smaller wires are more susceptible to opens or shorts due to stress and electromigration which are accelerated by heat and higher current density. Smaller device/circuit spaces are more susceptible to shorting from metal being extruded due to the above stresses.
Further, it is more important to screen as much of the chip as possible. As the use of on chip voltage generators and power save mode power headers become more prevalent, there is a need to provide a technique to screen “medium” level current defects behind these generators and headers.
Conventional current leakage screens performed in microelectronic testing typically have problems that are two fold: 1) at operating voltages there is low sensitivity to “medium” level shorts defects; 2) shorts defects can have such high current densities that parts of the redundant power and ground wiring can become ablated at operating or higher voltages thus decreasing the current pulled from the power supplies but still pull enough power to cause local heating. Large chips that draw a high current have less sensitivity to relatively small current shorts defects.
Currently, it is difficult to screen these “medium current” defects that do not cause functional or power limit fails while taking a minimum in yield loss. Thus it is necessary to find a method that enhances the ability to uniquely detect these defect's for screening with a minimum of yield loss from also screening non-reliability problem chips.
This can be especially problematic in arrays or other circuits where redundancy is employed to allow chips with defective arrays or circuits to be usable in the field. Redundancy allows chips with known electrically active defects to ship to the field. These defects can also be shorting circuits together and pulling substantial currents even if they are not needed for the chip to function.
Further, current techniques for testing for defects (current leakage) in IC's includes relying on gross probe check limits and Idd (quiescent current) limits at nominal voltages by voltage network and chips to functionally fail.